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�-� � D�<�lݞ�`�D�0TQ��	RR����h�L2���H@@��g@@��g@Q	NR�m�k����!�A�a��������;�$L2��@Q	��j�k��:�$L2����Z�L2��ݞ�AXI Bus monitor detect ! system: 0x%x ipc: 0x%x fetch addr: 0x%x
patch/wf_wm/sys_patch_mcu.caxi_mon_trigger == 0==>%s(), eMethod=%u eMsgId=%u
==>send, lp[%d]=0x%x    not zero
==>%s()
==>%s() mailboxCnt3=%u
NG prMsg = NULL mailboxCnt1=%u
==>recv, lp[%d]=0x%x   zero
NG lp[%d]=0x%x prMsg=0x%x
NGG mailboxCnt1=0 eMsgId=%u prMsg=0x%x
==>%s() mailboxCnt4=%u mboxidx=%u
==>%s() mailboxCnt1=%u
%s
0AXI_MON test handlerp_trace_strt123456789abcdef==>%s(), Done
;0x1806_016C = 0x%x ;0x8800_0444 = 0x%x ;0x8800_0430 = 0x%x ;0x8800_044C = 0x%x ;0x8800_0450 = 0x%x ;NMI status=0x%x WDT(to N9)
WDT(to Host)
From CCIF, host cpu sw interrupt for wakeup
APB/AHB bus timeout
From top, host cpu sw interrupt for wakeup
IDLM monitor
AXI monitor
;AXI Bus monitor detect ! system: 0x%x ipc: 0x%x fetch addr: 0x%x
access RAM error
wf_mcusys_vdnr_timeout_irq 
ENTRY_wsysMboxRcvAllMsgENTRY_wsysMboxSendMsgMCU_Patch_initENTRY_cos_set_reset_handler==>%s(), cr %x Done
Patch_HalPhyCalFuncpatch/common/sys_patch_common_efuse.cHLHL\cpu utlz trace
(cpu_utlz_cnt_%d)utlz=%d
inst:%d, total-access-time:%d, cache-misses:%d
CPI:, cache-miss-ratio: 
%u /%u -- %u/%u %u
show cpu utlz info:
CPU_UTLZ_CNT_BUSY_PCT_ADDR(0x%x)=%u
CPU_UTLZ_CNT_PEAK_BUSY_PCT_ADDR(0x%x)=%u
CPU_UTLZ_CNT_IDLE_CNT_ADDR(0x%x)=%u
CPU_UTLZ_CNT_PEAK_IDLE_CNT_ADDR(0x%x)=%u
CPU_UTLZ_CNT_MIN_IDLE_CNT_ADDR(0x%x)=%u
CPU_UTLZ_CNT_MEASURE_TIME_ADDR(0x%x)=%u
CPU_UTLZ_CNT_MAX_IDLE_CNT_ADDR(0x%x)=%u
g_mcu_real_clock_rate=%u
 start --> %s 
patch/common/sys_patch_common_mcu.c==>%s(), cmd=%x Done
Patch_dic_handler_extendcpu_utlz_cnt_testcpu_utlz_cnt_enablecpu_utlz_cnt_init;|<�����<�����
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